In recent years, in TFT substrates forming LCD devices, TFTs using a semiconductor layer comprised of an oxide semiconductor (hereinafter referred to as the “oxide semiconductor layer”) and having satisfactory characteristics such as high mobility, high reliability, and a low off-state current have been proposed as switching elements of pixels as a minimum unit of an image, instead of conventional TFTs using a semiconductor layer comprised of amorphous silicon (a-Si).
A typical TFT with a bottom gate structure includes a gate electrode formed on, e.g., a glass substrate, a gate insulating film provided so as to cover the gate electrode, a semiconductor layer provided on the gate insulating film so as to overlap the gate electrode, and source and drain electrodes provided on the gate insulating film so as to partially overlap the semiconductor layer with a gap between the source and drain electrodes, and a channel region is formed in a portion of the semiconductor layer which is exposed between the source and drain electrodes. A TFT using an oxide semiconductor layer also has a similar structure. In a TFT substrate, the TFT is covered by a protective insulating film, and a pixel electrode formed on the protective insulating film is connected to the drain electrode via a contact hole formed in the protective insulating film.
Such a TFT substrate having a TFT with a bottom gate structure can be manufactured by repeating a series of steps of sequentially forming an etching film by a sputtering method, a chemical vapor deposition (CVD) method, etc. and a photosensitive resin film by a coating method on, e.g., a glass substrate, exposing the photosensitive resin film via a photomask and then developing the photosensitive resin film to form a resist pattern, and patterning the etching film exposed from the resist pattern by dry etching or wet etching.
A channel etch TFT is known as such a TFT with a bottom gate structure. The number of photomasks required to form the channel etch TFT is smaller than that required to form an etch stopper TFT that includes a channel protective film functioning as an etch stopper, because the channel etch TFT does not have the channel protective film. Accordingly, the channel etch TFT is advantageous in terms of manufacturing cost. A channel etch TFT is also disclosed in, e.g., Patent Document 1 as a TFT using an oxide semiconductor layer.
Patent Document 1 discloses a configuration that uses an oxide semiconductor layer having a region where specific resistance varies in the thickness direction. In this configuration, the oxide semiconductor layer has lower specific resistance on the side of a gate insulating film than on the side of source and drain electrodes. Patent Document 1 describes that a TFT having stable characteristics such as a threshold voltage can be obtained by this configuration.